ASIC Physical Design Engineer

  • Company: Cisco
  • Posted: June 01, 2017
  • Reference ID: 1208196
Title: ASIC Physical Design Engineer
Location: San Jose, CA

Our creative and talented team as Physical Design lead in San Jose, CA. You will work with ASIC Front-end teams to understand chip architecture and drive physical aspects early in the design cycle, driving them to refine their design for physical design closure. As a member of this team you will be involved in creating cutting edge next generation networking chips. You will be the lead to drive the backend process through the entire Implementation flow including floor planning, Placement, CDC checks, static timing verification and equivalence checks, with special focus on power and die size optimization.


  • Responsible for floor planning , physical synthesis and physical design closure of large complex designs at 1GHz+ clock cycles
  • Responsible for driving timing closure through physical synthesis and Place & Route tools and working with ASIC vendors.
  • As member of physical/implementation design team, drive methodologies and "best known methods" to streamline physical design work, come up with guidelines and checklists and drive execution.
  • Work with Frontend team to understand the RTL design and drive physical aspects early in design cycle for physical design closure.
  • Resolve design and flow issues related to physical design, identify potential solutions


You are a HW engineer with 5+ years of related work experience with a broad mix of technologies including:
  • Excellent understanding of ASIC design methodologies from netlist to GDS
  • Familiar with all aspects of physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning.
  • Familiar with hierarchical design approach, top-down design, budgeting, timing constraints and physical convergence.
  • Hands on experience in block level implementation including physical synthesis, placement, routing and optimization with Innovus/ICC2 primetime and timing closure
  • Familiarity with low power design and custom placement implementation
  • Experience with large designs utilizing state of the art sub 16/14 nm technologies
  • Strong communication skills and ability to work as a team player

You should also have hands on experience with the following Tool sets
  • Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2
  • Synthesis Tools: Synopsys DC/DCG; Cadence Genus
  • Formal Verification : Synopsys Formality and Cadence LEC
  • Static Timing verification (Primetime/PTPX).
  • Familiarity with Physical Design Verification Flows is a plus.
  • Scripting: TCL, Perl is required; Python is a plus

Bachelor's or a Master's Degree in Electrical or Computer Engineering required

Why Cisco

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We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars. We celebrate the creativity and diversity that fuels our innovation. We are dreamers and we are doers.

We Are Cisco.

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