Design Verification Engineer- 1957969
Location:
San Diego , California
Posted:
December 15, 2017
Reference:
218479

SAN DIEGO , CA

Order: 218479

Job Title: Design Verification Engineer- 1957969

Location: San Diego, CA 92121

Schedule: Mon-Fri 8am-5pm

Duration: 12+ months

Pay: . DOE

Exempt

 

JOB OVERVIEW:

We are currently seeking digital verification engineers for the mixed-signal ASICs that support our mobile platforms for next generation 5G RFIC/PMIC/Codec technologies.
  • Successful candidates will be working on the following:
  • Block/Subsystem/SoC level digital IP verification using constraint-random coverage methodologies at both RTL and Gate Level.
  • The skills involved includes SV/UVM/UVM_REG/Randomization/Coverage/SVA.

QUALIFICATIONS:

Minimum Bachelors degree in Electrical Engineering or Computer Engineering
  • 3years minimum experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies.
  • : Extensive hand on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using regModel (UVM_REG) API, drivers, monitors, scoreboard, functional coverage (covergroups), assertions (SVA), simulations, regression, debug, bug reporting/tracking. -Experience in debugging RTL & Gate level simulations -Part of multiple tapeouts with high quality verification.


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