Digital Verification Engineer - 1962147
Location:
San Diego , California
Posted:
February 20, 2018
Reference:
219573

SAN DIEGO , CA

Order: 219573

Order Type : Temp - > 30 Hrs

Job Title: Digital Verification Engineer - 1962147

Duration: 12+ months

Pay: $50-$79/hr. (Depends on Experience Level II, III)

 

IMPORTANT:

Proven hands on experience in ASIC Verification, UVM, system Verilog assertions, gate level simulation, scripting using PERL or PYTHON.

Prior Experience in Phy layer verification, mixed signal verification, AMS verification is a plus.

 

Job Overview:
  • Currently seeking digital verification engineers for the mixed-signal ASICs that support mobile platforms for next generation RFIC/PMIC/Codec technologies.
  • Successful candidates will be working on the following:
  • Block/Subsystem/SoC level digital IP verification using constraint-random coverage methodologies at both RTL and Gate Level.
  • The skills involved include SV/UVM/UVM_REG/Randomization/Coverage/SVA.

 

Minimum Qualifications:
  • Minimum Bachelors degree in Electrical Engineering or Computer Engineering
  • 3years minimum experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies.

 

Preferred Qualifications:
  • Extensive hand on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using regModel (UVM_REG) API, drivers, monitors, scoreboard, functional coverage (covergroups), assertions (SVA), simulations, regression, debug, bug reporting/tracking.
  • Experience in debugging RTL & Gate level simulations
  • Part of multiple tapeouts with high quality verification.


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