SAN DIEGO , CA
Job Title: Design Verification Engineer- 1957381 (Digital IP Block Level Verification)
Location: San Diego, CA 92121
Schedule: Mon-Fri 8am-5pm
Duration: 6+ months
Pay: $50-$63/hr. DOE
Digital IP block level verification for RFFE
- Seeking digital verification engineers for the mixed-signal ASICs that support mobile platforms for next generation 5G RFIC technologies.
- Successful candidates will be working on the following:
- Block level digital IP verification using constraint-random coverage methodologies at both RTL and Gate Level.
- The skills involved includes SV/UVM/UVM_REG/Randomization/Coverage/SVA.
Required: Bachelor's, Computer or Electrical Engineering Preferred: Master's, Computer or Electrical Engineering
- 3 years minimum experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies.
- Extensive hands on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using regModel (UVM_REG) API, drivers, monitors, scoreboard, functional coverage (covergroups), assertions (SVA), simulations, regression, debug, bug reporting/tracking.
- Experience in debugging RTL & Gate level simulations
- Part of multiple tapeouts with high quality verification.
A little about us:
For nearly 70 years, Manpower’s mission is to provide job seekers with meaningful career opportunities.