The position is in Intel's Design for Test Engineering Group (DTEG), part of Platform Engineering Group (PEG). The Candidate would be focused on delivering DFT methodology through automation for leading edge SoC microprocessor designs
You will work with IP & integration design teams to understand the design and functional-mode behaviors of the logic & circuits. You will become familiar with the DFT designs of past Intel products to leverage their best-known methods and learn from their silicon experiences. Take those learnings, feed it back into the centralized dft team and deliver it to the other teams who would also benefit from the solutions.
You will assist in the RTL, schematic implementation, pre-silicon validation & post silicon debug of these DFT features. Come up with innovative solution to scan coverage issues and drive methodologies & automation for it. You will be expected to deliver high-quality documentation for consumption by the pre/post-silicon teams who will use the DFT features.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Degree in Electrical or Computer Engineering; MS with 2 years' experience/ BS with 5 years experience in RTL environments and/or silicon design/validation.
- Experience with RTL environments such as Verilog
- Experience with silicon design or validation
- Experience with SCAN, ATPG, MEMBIST, Array test, DFT methodology
Preferred Qualifications: MS in Electrical or Computer Engineering.
5 years in RTL environments and /or silicon design.
Extensive knowledge of the DFT concepts.
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