DFT Structural Design / STA Flow Development Engineer
Seeking a highly motivated, team-oriented engineer to drive development of Design for Test (DFT) insertion, synthesis, power optimization and timing analysis flows. In this position, you will be involved in the development and refinement of the physical construction and timing flows for DFT insertion into soft and hard IPs and SoCs, spanning from small IoT devices to large server processors.
The candidate should have experience in DFT, deep knowledge of scan insertion and ATPG methodology, memory test insertion and methodology. Knowledge of JTAG, 1687, boundary scan and IO testing would be a plus. Digital design experience related to SoC and IP design is required, especially in the areas of synthesis, timing analysis, power optimization, and clock tree construction. Seeking candidates with experience in DFT insertion and analysis tools such as DFT Compiler, Design Compiler, Power Compiler, Mentor Testkompress, Tessent Memory BIST, Primetime, ICC and clock tree synthesis. Ability to develop TCL based scripts for EDA DFT tools is required.
Minimum Qualifications and skills:
You should possess a Masters or Bachelor's degree in Electrical/Electronics/Computer Engineering, with 3 years relevant experience in the industry.
Candidate should have 3 years of experience with the following:
-Experience in circuit design fields: high-speed digital circuits, Timing analysis, and Power optimization.
Experience with VLSI circuit design fundamentals (CMOS, high-speed, low-power digital circuits; concept of timing and physical design convergence; layout knowledge).
-Experience in VLSI design, EDA synthesis tools and methodologies
DFT insertion, synthesis, power optimization and timing analysis
High-level programming skills of scripting languages (Perl, Python)
Experience with System on a chip integration
Knowledge of computer/CPU architecture
A little about us:
Our vision is simple and direct. If it computes, it does it best with Intel. We embrace all aspects of computing.