Digital Design Engineer 1958437/ 1958293
Location:
San Diego , California
Posted:
December 11, 2017
Reference:
218837

SAN DIEGO , CA

Order: 218837

Job Title: Digital Design Engineer for Mixed-Signal Application- 1958437/ 1958293

Location: San Diego, CA 92121

Schedule: Mon-Fri 8am-5pm

Duration: 3+ months

Pay: $63-79/hr. DOE

 

RESPONSIBILITIES:

Our team is actively looking for a Mid to high-level digital designer to work on next generation in-house development of digital SerDes designs.
  • This designer will be involved in delivering physical layer (PHY) designs for our industry leading wireless ICs, SOCs and chipsets. The designer will be part of a growing team and will be involved in next generation high-speed PHY architecture and development in state-of-the-art process technology nodes like 7nm CMOS and beyond.
  • Design goals also include the digital portion of low-power designs to address high data throughput PHY protocol requirements for our low-power wireless products.
  • The job function entails working within a very talented analog and mixed-signal circuit design team to deliver fully functional PHYs with SOC friendly digital interfaces and defect-free high- performance digital blocks to support analog design functions.

1)Participate in architecture definition and design of various SerDes PHYs (MIPI DPHY, MIPI DPHY, HDMI PHY, SATA PHY, PCIe PHY, USB PHY, etc)

2)Design digital portion of the PHYs using standard ASIC flow (micro-architecture definition, RTL coding, lint check, CDC check, DFT updates, Synthesis, Formal Equivalency Check, etc)

3)Debug and fix failing bugs reported by DV team, close functional bug tickets and write analysis reports 4)Work with Test Engineer for silicon debug in the Lab

 

Qualifications:

Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering and at least 2-3 years of experience are required in the following areas:
  • 1)ASIC design and verification 2)Knowledgeable in Physical Layer Protocol, experience in SerDes PHY development is a plus 3)ASIC EDA models and tools such as Design Compiler, Primetime, Tetramax, Radhawk, Spyglass, etc 4)Knowledgeable in transistor level design, ability to read Cadence schematics a plus 5)Knowledgeable in backend design process, able to work with PD team.
  • 1)Excellent verbal and written communication skills 2)Able to work with various teams across organization. 3)Fast learner and positive personality


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