Join the 5G mobile revolution at Intel as part of the Next Generation and Standards group. We are looking for design verification engineers at different levels including a DV team lead.
The team lead will provide technical leadership and the individual contributors will be part of a team that owns the full chip verification flow. The DV team is responsible for developing test plans in collaboration with design team and systems engineering, developing and maintaining verification environments, ensuring functionality and coverage goals are met and systematically executing on verification sign-off at IP, sub-system and SoC level.
- BSEE/MSEE and 8 years' experience in Verification and/or Design including the following:
- Hardware Verification Languages including System Verilog, Scripting Test Benches, OVM/UVM Methodologies and System Verilog Assertions.
- Digital Design and HDL's such as Verilog, VHDL and System Verilog.
- Scripting Languages such as Perl/tcl/Python/Gmake.
- Verification of SoC's with CPU, DSP or Micro-Controller Cores.
- Simulation Tools such as Simvision and Verdi.
- Cellular Wireless (LTE/UMTS) or 802.11/Wi-Fi Chipset Industry experience with verified Data Path Blocks (FFT's, Filters, Demodulator, Decoder, etc.)
- C with the ability to understand Reference Models.
- Solid understanding of Object Oriented Programming (OOP) Principles.
Additional Preferred Qualifications:
- Understanding of Bus Architectures (AXI or similar), Baseband/RFIC Interfaces, Network-on-Chip, various CPU/DSP Architectures, Multi-Domain Clocking and Power Management.
- Experience in developing and maintaining UPF Files for Power Analysis.
- Verification of Mixed-Signal IP's such as PLL's and LDO's.
- Understanding of Pre-Silicon Emulation for a Multi-Million Gate Count SoC. - Experience with tools like Palladium/Zebu.
A little about us:
Our vision is simple and direct. If it computes, it does it best with Intel. We embrace all aspects of computing.