IP Validation Engineer
Santa Clara , California
January 12, 2017
The EIG team within IPG is looking for an IP Validation Engineer in Santa Clara, CA.

This is a great opportunity for you to utilize your knowledge and talents in verification fundamentals and methodologies. Your unique strengths will be leveraged in validating IPs used in diverse products including servers, SoCs (System on a Chip), tablets, smartphones, desktops, wearable's & IOT. You will have opportunities to improve or define testbench architecture using industry standard verification methodologies such as OVM or UVM. You will collaborate closely with cross functional teams in delivering a Best in Class IP that is area & power optimized with challenging schedules.. You will support various product integration teams in integrating the IP under development. You will have an opportunity to collaborate with geo-diverse teams in analyzing, debugging and identifying the root cause of issues seen. We look forward to your innovative recommendations that accounts for technical and project constraints/requirements. This include developing a time based plan of action.

You will continuously learn, master and improve the current design, integration as well as validation activities that forms the IP flow via automation, scripting, fresh ideas and unconventional thinking. You will be given the opportunity to grow into a technical expert who is able to make an impact on a global level.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant previous school, industry jobs and/or research experience.

Minimum Qualifications:

Candidate must have a Bachelor's degree in Electronics, Computer or Electrical Engineering with 8 years of experience and relevant design verification experience.
Expertise in standard verification flows and processes, including constraint random verification, testplans, BFM (Bus Functional Models), verification infrastructure, test cases and functional coverage development.

  • Proficiency in OVM, UVM or VMM methodologies.
  • Experience in verifying complex, multi-clock and multi-power domain designs.
  • An ability to lead & collaborate with a diverse team in a dynamic work environment.
  • A love of problem solving and the motivation to stress test design with the goal of finding all possible design bugs.
Preferred Qualifications:

  • Validation Experience with computer architecture design, deep/machine learning, DSPs, caches, memory controller.
  • Protocol knowledge in I/O specifications such as IOSF, PCI, AXI, AHB, OCP, PIF.

A little about us:
Our vision is simple and direct. If it computes, it does it best with Intel. We embrace all aspects of computing.

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