SAN DIEGO , CA
Order Type : Temp - > 30 Hrs
Job Title: Low Power Design/Methodology Engineer -
Location: San Diego, CA 92121
Schedule: Mon-Fri 8am-5pm
Duration: 9 months
Pay: $63/hr.- $79/hr. DOE
Design low power / power management controller IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), on-chip sensor controller, digital power meter, and embedded voltage regulator controller.
- Design 3rd party PHY IP wrapper and IP landing.
- Provide SoC integration support.
- Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks.
- Work closely with technology/circuit design team to close IP block specification/requirement.
- Work closely with verification/physical design team to complete the IP design implementation.
- Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows.
- Work closely with system/software/test team to enable the low power feature in wireless SoC product.
- Evaluate new low-power technologies and analyze their applications to address requirements.
- Provide feedback for low-power chip and system architecture.
- Understand and perform block & chip-level power analysis. \Understand and create block-level power models.
Required: Bachelor's, Electrical or Computer Engineering
Preferred: Master's, Computer or Electrical Engineering
- 3 years of experience doing low power digital ASIC design.
- Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding, simulation, synthesis, STA.
- Previous experience in AVS (adaptive voltage scaling) desired.
- Understanding of electrical engineering concepts, circuit analysis and logic design skills.
- Familiarity with advanced low power techniques and high speed clocking desired.
- Proficiency in Verilog/System Verilog coding, verification techniques, and scripting language, such as: Perl, Python, Tcl, and Make etc.
- Good understanding of SoC architecture/micro-architecture.
- Strong debugging capabilities at simulation, emulation, and Silicon environments, including ability to design interesting debug experiments.
- Collaborate closely with cross-function team to research, design and implement performance and power management strategy for product roadmap.