SAN DIEGO , CA
Order Type : Temp - > 30 Hrs
Job Title: Physical Design Engineer
Location: San Diego, CA
- To do Floor planning, P&R, timing closure SI prevention/fixing, power planning, CTS, PV and I/R drop for Block as well as Top level MSM.
- Work on PD projects as needed
Required: Bachelor's, Computer Engineering Preferred: Master's, Computer Engineering
- Able to deal with MSM Top level complexity from FP, Placement, CTS, Routing and timing closure
- Must be able to take the Hardmacro through P&R from Netlist to GDS including timing closure, formal and Physical verification.
- Tools: EDA Physical design tools experience ( Examples: Cadence Innovas, Synopsys ICC2, PrimetimeSi/Calibre/ etc)
- Skills: Physical design implementation expertise in latest technology nodes in one of the below domains or all of these.
- Floorplanning at Full chip level or Macro or Block Level
- Macro placement, power grid implementation, power routing, special routing like analog signals, etc.
- Power collapse/Low power implementation flow
- Place and route at chip level or block level, perform placement, timing closure in P&R mode, perform clock tree synthesis , routing etc
- Timing closure/STA:
- Perform STA using primetimeSi or Tempus or any industry standard STA engine, timing closure, ECO generation, timing correlation
- Deep understanding of timing skills to perform correlation, timing fixes , corner/voltage definitions, etc.
- Clock Tree Synthesis:
- Perform custom or regular clock tree implementation at block level or top level.
- Clock tree balance of complicated tree, clock power reduction techniques etc
- Low Power Implementation:
- Power collapse/power gaing techniques/implementation
- UPF/CPF flow knowledge c.CLP/FV
- Physical Verification Using Calibre:
- Running all the PV checks (DRc/LVS/ERC/Softcheck )
- Deep understanding of all the rules and fixes
- Perl/Python/Shell script experience is also preferred to help with automation