Pre-Si Verification Engineer
Santa Clara , California
January 12, 2017
This opportunity is for a Pre-silicon Verification Engineer with the Platform Engineering group.
You will have an opportunity to develop pre-Silicon functional validation tests to verify system will meet design requirements. Create test plans for RTL validation, define and run system simulation models, find and implement corrective measures for failing RTL tests. You will analyze and use results to modify testing.
Minimum Qualifications

You must have a Bachelor's degree in Electrical engineering or computer engineering with 8 years of experience or MS in Electrical Engineering or Computer Science with at 6 least years of experience in ASIC Pre-silicon verification.

You must have a 5 years of experience with the following skills.

Strong working knowledge of System Verilog, and Object Oriented Programming techniques
Experience with VMM/OVM/UVM or similar
Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy or dve)
Knowledge and experience with Perl or similar scripting languages
Experience in architecting test bench environments for unit and system level verification

Preferred Qualifications:
Experience with configurable and reusable IP development
Experience with standard interface IP designs such as IOSF, IDI, etc. is a plus
Experience in working in an SoC environment is a plus
10 Years of relevant industry experience.

A little about us:
Our vision is simple and direct. If it computes, it does it best with Intel. We embrace all aspects of computing.

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