SDG VP of Design for Test for Central Engineering

  • Company: Intel
  • Location: Santa Clara, California
  • Posted: November 14, 2017
  • Reference ID: JR0044677

SDG VP of Design for Test for Central Engineering
Job Description
The Platform engineering group (PEG) is the innovation engine driving IP and products that fuel Intel's growth in Client, Datacenter, IOT and the virtuous cycle. Our mission is to efficiently deliver leadership performance products in Client, server, IOT, segment specific and custom designs that meet our quality, performance, schedule and cost commitments.

We are seeking a dynamic leader to lead the next wave of growth in Design for Test Central Engineering team for PEG. This leader will drive DFT design development and innovation activities globally working very closely with product development, automation and design, post silicon teams.

The successful candidate will: plan, provide resources for and direct activities in hardware and software Engineering functions to meet schedules, standards, and cost; cultivate and reinforce appropriate group values, norms and behaviors; identify and analyze problems, plans, tasks, and solutions; establish and oversee standards of excellence for group performance; provide guidance on employee development, performance, and productivity issues; use judgment on a variety of problems requiring deviation from standard practices. The team is primarily located in US, India, Israel and work closely with teams across Intel.

Responsibilities include:
  • DFT Technology development with SOC and IP DFT focus.
  • Key leadership role owning central DFT methodology and design engineering.
  • Optimize on cost, performance and TTM while leading complex product and IP portfolio across Datacenter, client, IOT and Automotive devices.
  • Managing DFT engineering projects, initiatives, and processes in alignment with PEG Engineering direction and commitments.
  • Developing the organization for sustained growth, and developing people for technical leadership and strong managers.
  • DFT Process improvement to improve efficiencies, in line with PEG Engineering goals for productivity & cost.
  • Proactively managing stakeholders in the product/IP development process with clear decision making and crisp communication to ensure the organization meets committed budget and plans.
  • Actively collaborating with PEG Engineering Staff, team members and other Intel groups in PEG
  • Influencing peers across planning / engineering to drive major initiatives in the interest of the overall business.
  • Be an effective ambassador for DFT central engineering as member of the overall PEG Engineering Leadership team.


Qualifications PhD or MS in EE, CE or CS with 15 years or more of Industry leading experience. Business acumen with at least 15 years of experience in the field and managed large, diverse, global teams. Proven track record working with senior leaders and principles to enable growth and overall convergence. Extensive knowledge of DFT architecture, IP/SOC, EDA, processor and ASIC implementations. Post Silicon debug experience. Well versed in Industry DFT platform tools.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel's next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Other Locations

Israel, Kiryat-Gat;US, Oregon, Hillsboro
Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
Position of Trust. This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Talent Consultant.

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