You will be joining the Client SoC Design team in the Devices Development Group, doing SoC design on Intel's latest generation process technology. Your primary responsibility will be designing SRAM and Caches on the leading 10nm process node for Client System on Chip designs.
You will closely collaborate with Process TD, Advanced Design, and SoC design teams across Intel on Cache/RF design methodology development. You will be steering next generation process/design co-optimization for Cache/SRAM designs. Expertise across domains spanning circuits, design, micro-architecture and CAD domains is required.
The ideal candidate will possess:
Excellent interpersonal and communication skills
Good understanding of overall CPU/SOC design cycle and requirements
The candidate should possess a BS, MS, or PhD in Electrical/Computer Engineering with experience in one or more of the following areas:
* 5 years 'experience in Cache/RF design
* 5 years' experience with Advanced Circuits (Libraries, SRAM, SER, RV)
* 3 years' experience in translating product requirements and process capabilities to implement cache designs for power/performance objectives within floorplan constraints
* 3 years' experience in timing analysis, such as Static Timing Analysis (Primetime), Timing verification and convergence, Race Analysis, and Variation analysis for design robustness
* 3 years' experience in DFX methodology, such as DFT and Coverage Analysis, Post Si Cache/SRAM characterization
* 3 years' experience in Design-Process Co-optimization (Transistor/Interconnect Definition/Optimization, RF/SRAM and Vmin optimization, Product Scaling, Cost)
* 3 years' experience in CPU/ASIC design methodology and flow development, especiallly in the RLS, Structural Design, APR & low power optimization domains
* 3 years' experience in programming in one or more of TCL, Perl, and Python
A little about us:
Our vision is simple and direct. If it computes, it does it best with Intel. We embrace all aspects of computing.