SoC - Low power design engineer
Santa Clara , California
January 12, 2017
Join the 5G mobile revolution at Intel as part of the Next Generation and Standards group.

As a member of the SOC/ASIC Design team, you will have responsibilities across all phases of SOC design. Including micro-architecture specification, design, and debug of complex logic for high performance, and low power design targets. You will own all aspects of development of large SOC blocks, including Internal and external IP integration, design of SOC system bus, and interface control logic.

This role will interface with other internal and external design groups. Participate in design/architecture reviews, work with DV team towards pre-silicon verification and flow automation, emulation and engage in post-silicon bring up activities. Scripting and programming experience using Perl, TCL, and Make.
Minimum Qualifications:
- BSEE/MSEE and at least 10 years' experience with the following:
- RTL Logic Design experience of Multi-Million Gate ASICs.
- Experience with High speed and Low Power Designs.
- Experience having power management architecture and power modeling

Preferred Qualifications:
- Proficiency in Front End Tools and Methodologies.
- Experience in VCS-NLP and UPF2.0
- Experience in low power verification and power intent verification
- Experience in power modeling and analysis with cellular modem and advanced technology nodes
- Experience with Multiple Clock Domains and Asynchronous Interfaces.
- Experienced in Synthesis Flows with Standard Libraries and different Process Nodes (e.g., 28nm, 22nm, 16nm/14nm, ...)
- Familiarity with Scripting Languages like Gmake/Perl/Tcl/Python.
- Experience with Bring Up and Lab Debug of Silicon.

A little about us:
Our vision is simple and direct. If it computes, it does it best with Intel. We embrace all aspects of computing.

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