Sr. Digital Design CAD Engineer
Location:
Posted:
October 22, 2016
Reference:
811439
As part of the Centralized Design Acceleration Organization under the NVM Solutions Group we seek experienced and a highly motivated Design Automation Champion to architect flows and methodologies for High Speed IC Designs to enable the next generation Silicon Photonics products. Silicon Photonics is the next wave of exciting fuelling growth prospect for the Data Center group. As a DA champion your responsibilities may include: Aiding design through creative automation techniques, enhancing infrastructure and contributing to design teams success to make the product successful. You may also be required to plan and organize design projects or phases of design projects and communicate status to upper management.
Qualifications:
Requirements:
You must possess a minimum of a
- Bachelor of Science degree in Electrical Engineering or Computer Engineering with at least 8-9 years of experience or
- Masters Degree in Electrical Engineering or Computer Engineering with at least 5-6 years of experience.

Qualifications

4 years experience in digital logic design Integrated Circuit (IC) tools (e.g. ICC/DC,primetime) and related methodologies and demonstrated experience with various Electronic Design Automation (EDA) tools, flows, and architecture.
Experience with developing/maintaining asic flows around ICC (or EDI/Innovus) and familiarity with different aspects of automation.
4 years experience in the RTL2GDS flow with exposure to DRC clean-up and converging designs .
- Demonstrates strong Tcl/Tk knowledge with good scripting, SKILL*, or Python/PERL, MAKE programming.
- Demonstrate experience to interface with engineers and managers by providing schedule updates and roadmap plans.
- Team player and self-motivated technical leader.

Additional Qualifications:
Experience in the below tools and corresponding methodologies is preferable
Frontend : Tensilica Xplorer, Synopsys VCS, Designware IP/VIP, Discovery Verification (OVM,UVM) Suite, Spyglass Lint
Backend : Synopsys Design Compiler, HSPICE, ICC - Power Planning, Floorplan, Place and Route, Clock Tree Synthesis
Sign-off Tools: RedHawk, PrimeTime, PrimeTime SI, Calibre LVS/DRC, Star XT.
Methodologies: Designware/Discovery OVM / UVM flows, Synopsys reference Flows, Low Power Methodology (UPF), MCMM flows.
A little about us:
Our vision is simple and direct. If it computes, it does it best with Intel. We embrace all aspects of computing.

Know someone who would be interested in this job? Share it with your network.