Intel Custom Foundry Group is Intel's exciting new venture into collaborating with Industry hardware leaders and bringing their products onto Intel's leading edge process technology. The ASIC design methodology team within Intel Custom Foundry is looking for talented individuals who wish to be a part of this experience of building the Industry's next generation products. As part of this fast growing design team, you will be working on leading edge System-on-Chip (SOC) designs from external customers. Your responsibilities include but are not limited to.
•Interface heavily with ASIC/SOC design teams to understand the design requirements and resolve flows and methodology issues related to fullchip floorplanning, fullchip integration, Hard-IP integration, layout verification, and tapeout. Help foundry customers take their next-generation SOCs to tapeout by sharing design methodology knowledge and experiences obtained through internal design execution.
•Take Intel's fullchip integration requirements into customer's fullchip designs. Review customer's floorplan for several key features at various milestones. Define the fullchip verification tapeout sign-off requirements.
•Lead the development of layout verification methodology and runset usage requirements and guidelines on Intel's latest process node. Address issues from foundry customers by collaborating with various internal support teams.
•Lead the development of the Hard-IP integration methodology concurrently with the IP development on the latest process node. Work with Hard-IP team to define the boundary conditions and specs while improving overall ease of integration and usability.
•Evaluate the next generation process technology challenges, primarily in physical-design and verification space, such as new DRC, density rules. Identify required future capabilities and new methodology definition for layout integration ahead of design start.
Bachelor or Master of Science degree in Electrical Engineering or Computer Engineering and at least 5 years of related industry experience.
Additional qualifications include:
•Demonstrate experience and hands-on practical knowledge with standard-cell based VLSI design methodology and relevant Synopsys or Cadence EDA tools (ICC, ICC-DP, ICV, Calibre, EDI)
•Demonstrate strong analytical and problem solving skills through relevant experiences with ASIC/SOC design convergence, Hard-IP integration, and fullchip layout verification and tapeout.
•Fullchip layout verification and tapeout experience on a leading process node.
•Demonstrate experience in scripting with Unix shell, Perl and TCL.
A little about us:
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