Our team is part of IPG- PEG and we currently have an opportunity for a Test Chip Architect.
Your responsibilities include but are not limited to:
Determine, specify and evaluate the viability of complex hardware features and structures and ensure that software and hardware designs interface correctly. You will Identify, analyze and resolve sub-system and/or chip-level architecture and design challenges. You will have an opportunity to influence the shaping of future products by significantly contributing to the architecture used across IPs and chip families. Provide multi-layered technical expertise for next generation initiatives. You will Lead chip execution from a technical and leadership role to ensure the architecture can be properly implemented and adjustments made when needed. You will function as decision maker across the Platform Product Life Cycle. You will manage strong partner teams which include IP team, SoC teams, platform teams and post-silicon teams.
Behavioral traits for this position include:
Must be a very good communicator, and delivers consistently exceptional results.
The successful candidate will play a key role in leading the transformation of Intel from a product-focused to a platform-focused organization.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant previous school, industry jobs and/or research experience.
Candidate must have a Bachelor's degree with 8 years of experience or a Master's degree (MBA/ MS) with at 6 least years of experience in the hi-technology industry.
Experience in multiple chip architecture definitions and hands on execution involving multiple SoCs.
Good documentation skills and good analytical skills to present a complete technical proposal and architecture.
Ability to involve in driving and hands on executing in multiple phases of a SoC design such as RTL design, RTL integration, RTL verification, timing constraints, floorplan, DFT, board design and post-silicon testing.
Knowledge of industry standard protocols such as USB, PCIe, DP, MIPI, AMBA, etc.
Knowledge of pre- and post-silicon validation strategies.
Ability to work with partner teams to coordinate technical requirements and execution."
12 Years of relevant industry experience
Experience with SOC Design, Chip Architecture
A little about us:
Our vision is simple and direct. If it computes, it does it best with Intel. We embrace all aspects of computing.